法国专利FR3017261A1

专利PDF首页>>法国专利

专利附录

专利说明

权利要求

类似技术

同族专利

引用文献

法律状态

优先权

专利摘要:
Embodiments include apparatus, system and method related to a switching circuit. In some embodiments, the switching circuit may include a first switch including a field effect n-channel (FET) transistor in the signal path. The switching circuit may further comprise a second shunt switch to the first switch. The second switch may include a discharge transistor (132) for providing a discharge path for a body (120) of a switching transistor (104).
公开号:FR3017261A1
申请号:FR1550755
申请日:2015-01-30
公开日:2015-08-07
发明作者:George Nohra
申请人:Triquint Semiconductor Inc；
IPC主号:

专利说明:

[0001] FIELD EFFECT TRANSISTOR SWITCHING CIRCUIT Embodiments of the present invention generally relate to the field of circuits, and more particularly to switching circuits. Field Effect Transistors (FETs) can be used for low-power radio frequency (RF) switching devices, particularly in mobile applications where price, performance, and power consumption are key. However, FETs can present difficulties when dealing with larger signals. In particular, the performance under large signals in FETs acting as switches can be affected by charge accumulation in a quasi-neutral region of the FET body.
[0002] Load build-up can result in hot carrier build-up, excessive gate induced drain leakage (GIDL), negative transconductance, grid gate loss, etc. These problems can usually be called Floating Body Effect (FBE). In some applications, some applications may require ultra-fast switches, and ultra-low loss / high isolation. In some cases, a low loss switch may require a negative voltage generator (NVG) that can be used to achieve the required low loss and isolation, and also to meet the requirements of large signals. However, the use of NVG can result in a slower switch, as well as high indirect costs in terms of circuit area. In addition, the use of NVG can cause a leakage current in the sleep mode, ie when the circuit does not actively transfer a signal. In some cases, blocking capacitors may be used in the switches to address the problems described above, however the use of blocking capacitors may result in a large circuit area and also reduce circuit performance. For example, the circuit may experience poor insertion loss, poor linearity, and / or poor isolation. According to a first aspect, the invention relates to a switching circuit comprising: a first switch including an n-channel transistor; and a second switch coupled to the first switch, the second switch including: a first p-channel transistor including a first source contact, a first drain contact, a first gate contact, and a first body contact; a second p-channel transistor coupled to the first p-channel transistor, the second p-channel transistor including a second source contact, a second drain contact, a second gate contact, and a second body contact, wherein the first p-channel transistor gate contact is coupled to the second drain contact, and the first body contact is coupled to the second source contact; and a first resistor and a second resistor both coupled to the second gate contact. Advantageously, one or more of the following arrangements can be used in this first aspect of the invention: the first resistance or the second resistance is a high density resistor; the first p-channel transistor has a thickness of 1 millimeter (mm); the second p-channel transistor has a thickness of 3 micrometers (11m); the first source contact is coupled to a third switch which includes at least a third p-channel transistor and a fourth p-channel transistor; the first gate contact is coupled to a DC voltage input source (CC); the first switch is coupled to the second switch so that the first p-channel transistor is directly coupled to the first switch and the first p-channel transistor is between the first switch and a ground contact of the switching circuit. According to a second aspect, the invention relates to a method comprising: coupling a gate contact of a first p-field effect (FET) transistor to a drain contact of a second p-channel FET coupling a body contact of the first p-channel FET to a source contact of the second p-channel PET; coupling a gate contact of the second p-channel FET to a first resistor and a second resistor; and coupling a drain contact of the first p-channel FET and the first resistor to an n-channel FET so that the first p-channel FET is electrically positioned between the n-channel FET and a ground. Advantageously, one or more of the following arrangements can be used in this second aspect of the invention: the first resistance or the second resistance is a high density resistor; the first p-channel FET has a thickness of 1 millimeter (mm); the second p-channel PET has a thickness of 3 micrometers (Iim); the first p-channel FET, the second p-channel FET, the first resistor, and the second resistor are a first switch, and a source contact of the first p-channel FET is coupled to a second switch which includes a third one; FET with p channel. According to a third aspect, the invention relates to a system comprising: a signal input; a first switch electrically positioned between the signal input and a signal output, the first switch including a field effect n-channel (FET) transistor; and a second switch electrically coupled between the signal input and a ground, and electrically coupled between the first switch and the ground, wherein the second switch includes: a first p-channel FET; A second p-channel FET coupled to the first p-channel FET, the second p-channel FET including a drain contact coupled to a gate contact of the first p-channel PET, and a source contact coupled to a body contact the first p-channel PET; and a first resistor and a second resistor both coupled to a gate contact of the second p-channel FET. Advantageously, one or more of the following arrangements may be used in this third aspect of the invention - the first or second resistor is a high density resistor; the first p-channel FET has a thickness of 1 millimeter (mm); the second p-channel FET has a thickness of 3 micrometers (lam); the system further comprises a third switch which includes a third p-channel FET and a fourth p-channel FET, wherein a source contact of the first p-channel FET is coupled to a drain contact of the third p-channel FET . Embodiments are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings, in which like references indicate similar elements and in which: FIG. 1 illustrates a field effect transistor switch ( FET) according to various embodiments. Figure 2 illustrates a switching circuit incorporating a plurality of switches according to various embodiments. Fig. 3 illustrates an illustrative method of constructing a switching circuit according to various embodiments. Fig. 4 is a block diagram of an illustrative wireless communication device according to various embodiments. Embodiments include a switching circuit. In some embodiments, the switching circuit may include a first switch that includes an n-channel switching transistor in the signal path. The n-channel switching transistor may be a field effect n-channel (FET) transistor. The switching circuit may further comprise a second shunt switch to the first switch. The second switch may include a switching transistor and a discharging transistor for providing a discharge path for a body of the switching transistor. The switching transistor and the discharge transistor may be p-channel transistors, and more specifically, p-channel FETs. Both the n-channel transistor and the p-channel transistors 30 may be coupled to a voltage source configured to provide a positive voltage to the switches. When the voltage source supplies the positive voltage, the switch that includes the n-channel switching transistor may light so that the switch can allow a radio frequency (RF) signal to propagate through the switch. At the same time, the switch that includes the p-channel transistors may go out due to the positive voltage. The positive voltage can then be eliminated, or a negative voltage can be applied, and the switch that includes the n-channel transistor can be turned off while the switch that includes the p-channel transistors turns on. Other embodiments may be described and claimed. Various aspects of the illustrative embodiments will be described using terms commonly used by those skilled in the art to communicate the substance of their work to another skilled in the art. However, it will be obvious to those skilled in the art that other embodiments can be practiced with only some of the described aspects. For explanatory purposes, specific devices and configurations are presented to provide a thorough understanding of the illustrative embodiments. However, it will be obvious to those skilled in the art that other embodiments can be practiced without specific details. In other cases, well-known features are omitted or simplified so as not to complicate the illustrative embodiments. In addition, various operations will be described in the form of multiple distinct operations, in turn, in a manner that is most useful in understanding the present invention; however, the order of description should not be interpreted as implying that these operations are necessarily dependent. In particular, these operations do not need to be performed in the order of presentation. The expression "in one embodiment" is used repeatedly. The expression does not generally refer to the same embodiment; however, she can. The terms "comprising", "including" and "including" are synonymous unless the context requires otherwise. To provide context for language clarification that may be used in conjunction with various embodiments, the terms "A / B" and "A and / or B" mean (A), (B), or (A and B) ; and "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C) or (A, B and VS). The term "coupled to", together with its derivatives, may be used herein. "Coupled" can mean one or more of the following. "Coupled" can mean that two or more elements are in physical or direct electrical contact. However, "coupled" may also mean that two or more elements come into contact indirectly, and yet still cooperate or interact, and may mean that one or more other elements are coupled or connected between the elements that are said to be coupled together. to each other.
[0003] Figure 1 illustrates a switch 100 according to various embodiments. The switch 100 may be a silicon on insulator (SOI) device comprising a silicon layer disposed on an insulating layer, which may also be called buried oxide layer (BOX). In some embodiments, an additional silicon layer may be disposed beneath the insulating layer. In various embodiments, the upper silicon layer may be approximately 50 to 90 nanometers (nm) thick and the insulating layer, which may be a layer of silicon dioxide or sapphire, may be approximately 100 to 200 nm thick. 'thickness. In some embodiments, the switch 100 may be a partially depleted SOI device (PDSOI) in which the silicon under a doped layer is partially depleted of free charge carriers. The partially depleted zone may be called a quasi-neutral region. The switch 100 may comprise a switching transistor 104. In some embodiments, the switching transistor 104 may be a field effect transistor (NET). In some embodiments, the switching transistor 104 may have a tendency to accumulate charges in the near-neutral region, as described above. Embodiments described herein permit the discharge of these accumulated charges while reducing at least some of the problems identified above related to other techniques designed to address the problems of BPT. The switching transistor 104 may include a gate contact 108, a source contact 112, a drain contact 116, and a body contact 120. The switch 100 may further include resistors 124 and 128 coupled in series with each other. with each other and further coupled to and between the source contact 112 and the drain contact 116, as shown. Resistors 124 and 128 may be of equal size in some embodiments. In some embodiments, the resistors 124 and 128 may be high density resistors. In some embodiments, the resistors 124 and 128 may be coupled by a control line 129. The switch 100 may further include a resistor 130 coupled to the gate contact 108. The switch 100 may further include a discharge transistor 132 In some embodiments, the discharge transistor 132 may be a FET. The discharge transistor 132 may operate to create a discharge path for discharging charges that accumulate in the near-neutral region of the switching transistor 104. The discharge transistor 132 may comprise a gate contact 136, a contact source 140, and a drain contact 144. The gate contact 136 may be coupled to a node 148 which is located between the resistors 124 and 128; the source contact 140 may be coupled to the contact body 120; and the drain contact 144 may be coupled to the gate contact 108. The resistors 124 and 128 may provide a virtual ground, for example, a fixed potential, at the node 148 and, therefore, at the gate contact 136. The use of the discharge transistor 132 to attach the contact body 120, the drain contact 116, and the source contact 112 to the fixed potential of the node 148 can facilitate the elimination of the potential difference between the gate contact 108. and the contact body 120 and, therefore, discharging charges from the quasi-neutral region. In some embodiments, the drain contact 116 may be coupled directly or indirectly with a radio frequency (RF) signal input terminal 152 through which the switch 100 may receive an RF signal. The source contact 112 may be coupled directly or indirectly with an RF signal output terminal 156 from which the RF signal may be sent by the switch 100. The gate contact 108 and / or the drain contact 144 may be coupled directly or indirectly with a voltage source 160, which can provide a control voltage to turn on or off the switching transistor 104 and the discharge transistor 132, as described below. In embodiments, the switch 100 may operate as follows. It should be noted that the description below assumes that the switching transistor 104 and the discharging transistor 132 are both 30 n channel FETs. However, as described in more detail below, in some embodiments, the switching transistor 104 and the discharging transistor 132 may both be p-channel FETs, in which case the operation may be reversed.
[0004] Initially, the switch 100 may be turned on by turning on the switching transistor 104 to pass a signal, for example, the radio frequency (RF) signal received from the RF signal input terminal 152, the drain contact 116 In some embodiments, the switching transistor 104 may be turned on by applying a positive DC voltage, for example, 2.5 volts (V), to the gate contact 108 of the switching transistor. 132, for example by applying the positive DC voltage from the voltage source 160. The drain contact 144 of the discharge transistor 132 will also know the positive DC voltage. The gate contact 136 of the discharge transistor 132 may experience a voltage 0 to the virtual earth. This can cause a gate-source voltage, V_gs, of -2.5 V at the discharge transistor 132. This will turn off the discharge transistor 132 and, in fact, eliminate the discharge transistor 132 from the circuit switch. In some embodiments, the switch 100 may be turned off to provide a discharge path between the gate contact 108 and the contact body 120 of the switching transistor 104. In some embodiments, the switch 100 may be turned off by turning off the switching transistor 104 for preventing the passage of a signal, for example, the RF signal received from the RF signal input terminal 152, from the drain contact 116 to the source contact 112. In some embodiments, the switching transistor 104 may be extinguished by applying zero DC voltage or a negative DC voltage, for example, 0 V or -2.5 V, to the gate contact 108 of the switching transistor 104. The drain contact 144 of the discharge transistor 132 may also know the negative DC voltage. This can cause a positive V_gs, for example 2.5 V, at the discharge transistor 132. This can turn on the discharge transistor 132, thereby creating a discharge path by coupling the gate contact 108 of the switching transistor 104. to the contact body 120 of the switching transistor 104. This can be done without having to provide a voltage safety margin because there will be no threshold voltage drop. Although the operation of the switch 100 is generally described in terms of using an n-channel FET as a switching transistor 104 (also referred to as an "NMOS switch" or "NMOS transistor"), embodiments using a p-channel transistor such as p-channel FET as switching transistor 104 (also referred to as PMOS switch or PMOS transistor) and discharge transistor 132 may be used. In embodiments where the switching transistor 104 and the discharge transistor 132 are p-channel transistors, applying a positive voltage may cause the p-channel transistors to go off while the application negative voltage or zero voltage can cause the n-channel transistors to light up. Providing a discharge path using switch 100 as described above may not result in the same penalty associated with a voltage threshold safety margin that is associated with a PET switch circuit connected by diode. Illustrative simulations have shown that, with respect to a diode-connected FET switch circuit, the switch 100 can be associated with a 3 dB improvement over the IMD, a 2.5 dB improvement over third-order harmonics, and a 1.5 dB improvement over second-order harmonics. Providing a discharge path using switch 100, as described above, can also result in the same penalty related to insertion loss that is associated with a body contact (BC) switching circuit. resistive. Illustrative simulations have shown that, with respect to a resistive BC switching circuit, the switch 100 may be associated with an improvement of 40 millidecibels (mdB) or more over the insertion loss, an improvement of 1 dB over at IMD, a 3.5 dB improvement over second-order harmonics, and an improvement of 0.5 dB over third-order harmonics. The switch 100 may be a common gate amplifier and may be incorporated in a variety of applications including, but not limited to, complementary metal oxide semiconductor (CMOS) switches, power amplifiers, low noise amplifiers (LNAs), buffer circuits, duplexers, etc. In some embodiments, a plurality of switches 100 may be incorporated into a single circuit design. Figure 2 illustrates an example of a switching circuit 200 incorporating one or more switches, each of which may be similar to the switch 100 described above. Specifically, the switching circuit 200 may comprise switches 204 and 208. The switches 204 and 208 may be coupled to, and generally positioned between, an RF signal input 212 and an RF signal output 216, which may be respectively similar to the RF signal input 152 and the RF signal output 156. The switches 204 and 208 may respectively be similar to the switch 100 described above, and both the switching transistors and the switching discharge transistors 204 and 208 may be n-channel transistors, and more specifically n-channel 1, AND, as described above. As shown in Fig. 2, the switches 204 and 208 may be coupled to each other in series so that the source contact of the switching transistor of the switch 204 is coupled to the drain contact of the switching transistor. of the switch 208. In embodiments, the switches 204 and 208 may be coupled to a voltage source 220 configured to provide a positive voltage, for example 2.5 V. In some embodiments, a resistor 224 may be positioned generally between the voltage source 220 and the switches 204 and 208. In some embodiments, the resistor 224 may include a control line 228. In embodiments, the voltage source 220 may be similar to the voltage source. 160, described above. The switching circuit 200 may comprise additional switches 232 and 236. The switches 232 and 236 may be generally positioned between the RF signal input 212 and the earth 240. Specifically, it can be said that the switches 232 and 236 are shunt of the switching circuit 200.
[0005] In embodiments, the switches 232 and 236 may be coupled to a voltage source 244 configured to provide a positive voltage, for example 2.5 V. In some embodiments, the voltage source 244 and the voltage source 220 may be the same voltage source, or otherwise be coupled to each other. In some embodiments, a resistor 248 may be positioned generally between the voltage source 244 and the switches 232 and 236. In some embodiments, the resistor 248 may include a control line 252.
[0006] The switches 232 and 236 may respectively be similar to the switch 100 described above, and both the switching transistors and the switch discharge transistors 232 and 236 may be p-channel transistors and, more specifically, FETs to channel p, as described above.
[0007] As shown in FIG. 2, the switches 232 and 236 may be coupled to each other in series so that the source contact of the switching transistor of the switch 232 is coupled to the drain contact of the switching transistor. 236. Although the switching circuit 200 is described with two switches 204 and 208 with the n-channel transistors, and two switches 232 and 236 with the p-channel transistors, in other embodiments, the circuit switching may have more or fewer switches. In some embodiments, the switches 204 and 208 may include p-channel transistors and the switches 232 and 236 may include n-channel transistors, and the voltage source 220 and 224 may be configured to provide a negative voltage. In operation, the switching circuit 200 may operate as follows. An RF signal may be provided at the RF signal input 212. A positive voltage may be provided at the voltage sources 220 and 244. As described above, the switches 204 and 208 may include FET n channel. When the switches 204 and 208 receive the positive voltage from the voltage source 220, the discharge transistors of each of the switches 204 and 208 may turn off. Further, the switch transistors can light up so that the RF signal can propagate through the switching circuit 200 of the RF signal input 212 to the RF signal output 216. Similarly, the switches 232 and 236 may receive a positive voltage from the voltage source 244. As described above, the switches 232 and 236 may include p-channel FETs. Thus, the positive voltage received from the voltage source 244 can cause the switch transistors of the switches 232 and 236 to go off. When the switch transistors of the switches 232 and 236 are off, a signal may be unable to propagate from the RF signal input 212 to the ground 240. Thus, the shunt portion of the switching circuit 200 may actually be closed by the application of a positive voltage, while this signal portion of the switching circuit 200 can be opened by the positive voltage. On the other hand, the application of zero voltage, or ground voltage, from the voltage sources 244 and 220 can cause the switching circuit 200 to operate in an opposite manner as described above. above. Specifically, the application of the ground voltage from the voltage source 220 may cause the switch discharge transistors 204 and 208 to be on, so that signals may be grounded 240. For example, the noise from the RF signal input 212 may be shunted to earth 240. At the same time, the switching transistors of the switches 204 and 208 may be turned off so that the noise from the RF signal input 212 may not propagate to the RF signal output 216. The switching circuit described above 200 can enjoy several advantages. Specifically, the switching circuit 200 may have improved insertion loss, and greater insulation and overall performance, while still residing in a relatively compact area. For example, in some embodiments, a switching transistor of a switch may have a thickness of approximately 1 millimeter (mm). A discharge transistor of a switch may have a thickness of approximately 1 micron (jam). In addition, the switching speed of the switching circuit 200 can be considered to be very fast. Further, the switching circuit 200 may be implemented using only positive voltage sources, such as the voltage sources 220 and 244, which in some embodiments may be combined into a single positive voltage source. . Therefore, the switching circuit 200 may not require blocking capacitors or negative voltage generator. Fig. 3 illustrates an illustrative method for constructing a switching circuit, such as switching circuit 200. Initially, the gate contact of a first transistor may be coupled to the drain contact of a second transistor 30 to 304. Specifically, , the gate contact of a switching transistor, such as the switching transistor 104 of a switch 100 in a switch, such as the switch 232, may be coupled to the drain contact of a discharge transistor, such as the discharge transistor 132 in the switch 232.
[0008] Then, a body contact of the first transistor may be coupled to a source contact of the second transistor at 308. Specifically, the contact body of the switching transistor 104 of a switch 100 in the switch 232 may be coupled to the source contact of the switch. discharge transistor 132 in switch 232. Then, the gate contact of the second transistor may be coupled to a first resistor and a second resistor 312. Specifically, the gate contact of discharge transistor 132 in switch 232 may be coupled. resistors, such as the resistors 124 and 128, so that the gate contact 136 knows a virtual ground. Finally, the drain contact of the first transistor may be coupled to a second switch. For example, the drain contact of the switching transistor 104 of a switch 100 in the switch 232 may be coupled to another switch, such as the switch 204. Specifically, the drain contact of the switching transistor 104 in the switch 232 can be coupled to the drain contact of the switching transistor in the switch 204. As noted above, the discharge transistor and the switching transistor of the switch 232 may be p-channel FETs, while the switching transistor of the switch 204 may be an n-channel FET.
[0009] The switch 200 may be incorporated in a variety of systems. A block diagram of an illustrative system 400 is illustrated in Figure 4. As illustrated, the system 400 includes a power amplifier (PA) module 402, which may be a radio frequency (RF) PA module in some embodiments. The system 400 may include a transceiver 404 coupled to the PA module 402, as illustrated. The PA module 402 may include the switching circuit 200 for performing any of a variety of operations such as amplification, switching, mixing, etc. In various embodiments, the switching circuit 200 may further optionally be included in the transceiver 404 to provide, for example, upconversion, or in an antenna switch module (ASM) 406 for provide various switching functions. The PA module 402 can receive an RF input signal RFin from the transceiver 404. The PA module 402 can amplify the RF input signal RFin to provide the RF output signal RFout. The RF input signal, RFin, and the RF output signal, RFout, may both be part of a transmission chain, respectively denoted by Tx-RFin and Tx-RFout in Fig. 4. The output signal RF amplified, RFout, may be provided to ASM 406, which performs radio over-the-air (OTA) transmission of the RF output signal, RFout, through an antenna structure 408. The ASM 406 may also receive RF signals through the antenna structure 408 and couple the received RF signals, Rx, to the transceiver 404 along a reception chain. In various embodiments, the antenna structure 408 may include one or more directional and / or omnidirectional antennas, including, for example, a dipole antenna, a monopole antenna, a plate antenna, a loop antenna, an antenna microstrip or any other type of antenna suitable for OTA transmission / reception of RF signals. The system 400 may be any system including power amplification. In various embodiments, the inclusion of the switching circuit 200 in the system 400 to switch the RF signal may be particularly useful when the system 400 is used for high power and RF power amplification. For example, the inclusion of the switching circuit 200 in the system 400 may be particularly advantageous for the transmission of global mobile communication system (GSM) signals with a power of approximately 32 dBm or more and a frequency of approximately 1800 megahertz (MHz) or more, as well as lower band GSM signals, for example 800 MHz to 915 MHz, having a power of approximately 34 dBm or more.
[0010] The system 400 may be suitable for any one or more terrestrial and satellite communications, radar systems, and possibly various industrial and medical applications. More specifically, in various embodiments, the system 400 may be selected from a radar device, a satellite communication device, a mobile computing device (e.g., a phone, a tablet, a laptop computer, etc.), a base station, broadcast radio, or television amplifier system. Although the present invention has been described with respect to the embodiments illustrated above, one of ordinary skill in the art will appreciate that a wide variety of other and / or equivalent implementations, calculated to achieve the same objectives, may be substituted for the specific embodiments presented and described, without departing from the scope of the present invention. Those skilled in the art will readily appreciate that the teachings of the present invention can be implemented in a wide variety of embodiments. This description is intended to be illustrative and not restrictive.

权利要求:
Claims (17)
[0001]
REVENDICATIONS1. A switching circuit (200), comprising: a first switch (204, 208) including an n-channel transistor; and a second switch (204, 208) coupled to the first switch (204, 208), the second switch (204, 208) including a first p-channel transistor (104) including a first source contact (112), a first contact drain (116), a first gate contact (108), and a first body contact (120); a second p-channel transistor (132) coupled to the first p-channel transistor (104), the second p-channel transistor (132) including a second source contact (140), a second drain contact (144), a second gate contact (136), and a second body contact, wherein the first gate contact (108) is coupled to the second drain contact (144), and the first body contact (120) is coupled to the second earth contact (144). source (140); and a first resistor (124) and a second resistor (128) both coupled to the second gate contact (136).
[0002]
The switching circuit (200) of claim 1, wherein the first resistor (124) or the second resistor (128) is a high density resistor.
[0003]
The switching circuit (200) of claim 1, wherein the first p-channel transistor (104) has a thickness of 1 millimeter (mm).
[0004]
The switching circuit (200) of claim 1, wherein the second p-channel transistor (132) has a thickness of 3 micrometers (μm).
[0005]
The switching circuit (200) of claim 1, wherein the first source contact (112) is coupled to a third switch (232, 236) which includes at least a third p-channel transistor and a fourth channel transistor p.
[0006]
The switching circuit (200) of claim 1, wherein the first gate contact (108) is coupled to a DC voltage input source (CC) (160).
[0007]
The switching circuit (200) of claim 1, wherein the first switch (204, 208) is coupled to the second switch (204, 208) so that the first p-channel transistor (104) is directly coupled to the first switch (204, 208). switch (204, 208) and the first p-channel transistor (104) is between the first switch (204, 208) and a ground contact of the switching circuit (200). 10
[0008]
A method (300), comprising: coupling (304) a gate contact (108) of a first field effect p channel transistor (FET - 104) to a drain contact (144) of a second p-channel FET (132); Coupling (308) a body contact (120) of the first p-channel FET (104) to a source contact (140) of the second p-channel FET (132); coupling (312) a gate contact (136) of the second p-channel FET (132) to a first resistor (124) and a second resistor (128); and coupling (316) a drain contact (116) of the first p-channel FET (104) and the first resistor (124) to an n-channel PET such that the first p-channel FET (104) ) is electrically positioned between the n-channel FET and a ground.
[0009]
The method of claim 8, wherein the first resistor (124) or the second resistor (128) is a high density resistor. 25
[0010]
The method of claim 8, wherein the first p-channel FET (104) has a thickness of 1 millimeter (mm).
[0011]
The method of claim 8, wherein the second p-channel FET (132) has a thickness of 3 micrometers (μm).
[0012]
The method of claim 8, wherein the first p-channel FET (104), the second p-channel FET (132), the first resistor (124), and the second resistor (128) are a first switch, and a The source contact (112) of the first p-channel PET (104) is coupled to a second switch that includes a third p-channel FET.
[0013]
A system (400), comprising: a signal input (RFin); a first switch electrically positioned between the signal input (RFin) and a signal output (RFout), the first switch including a field effect n-channel (FET) transistor; and a second switch electrically coupled between the signal input (RFin) and a ground, and electrically coupled between the first switch and the ground, wherein the second switch includes: a first p-channel PET (104); a second p-channel PET (132) coupled to the first p-channel NET (104), the second p-channel PET (132) including a drain contact (144) coupled to a gate contact (108) of the first p-PET p channel (104), and a source contact (140) coupled to a body contact (120) of the first p-channel FET (104); and a first resistor (124) and a second resistor (128) both coupled to a gate contact (136) of the second p-channel FET (132).
[0014]
The system of claim 13, wherein the first resistor (124) or the second resistor (128) is a high density resistor.
[0015]
The system of claim 13, wherein the first p-channel FET (104) has a thickness of 1 millimeter (mm).
[0016]
The system of claim 13, wherein the second p-channel NET (132) has a thickness of 3 micrometers (μm). 30
[0017]
The system of claim 13, further comprising a third switch which includes a third p-channel FET and a fourth p-channel FET, wherein a source contact (112) of the first p-channel PET (104) is coupled at a drain contact of the third p-channel PET.

类似技术:

公开号 | 公开日 | 专利标题

FR3017261A1|2015-08-07|

TWI595751B|2017-08-11|Body-contacted partially depleted silicon on insulator transistor

US20110221519A1|2011-09-15|Semiconductor integrated circuit and high frequency module using the same

US9214932B2|2015-12-15|Body-biased switching device

US9246483B2|2016-01-26|High-frequency switching circuit

JP4308251B2|2009-08-05|Antenna switch including field effect transistor

KR102312044B1|2021-10-12|Bias-boosting bias circuit for radio frequency power amplifier

KR101571280B1|2015-11-24|Diode, circuit employing the same and methods of manufacture

FR2906655A1|2008-04-04|Complementary metal oxide semiconductor | radio frequency | antenna switch used in wireless communication has receiver switch having transistors including first transistor with body substrate

US20060009164A1|2006-01-12|Radio frequency switching circuit

FR2909497A1|2008-06-06|SYSTEMS, METHODS AND APPARATUS FOR HIGH-POWER CMOS ANTENNA SWITCHES USING BODY SWITCHING AND SUBSTRATE-CONNECTED DIODE SWITCHING IN MULTI-STACK STRUCTURE

FR2994621A1|2014-02-21|NON-NEGATIVE POLARIZATION SWITCHING DEVICE

US10483960B2|2019-11-19|Radio frequency switch with low oxide stress

FR3011150A1|2015-03-27|ELECTROSTATIC DISCHARGE CIRCUIT

US20140171010A1|2014-06-19|Semiconductor Devices with Switchable Ground-Body Connection

Wu et al.2015|19.5 An HCI-healing 60GHz CMOS transceiver

US8598951B1|2013-12-03|Linear multi-mode power amplifier for dynamic supply operation

CN113114297A|2021-07-13|Transceiver front-end with receiver branch matching network including integrated electrostatic discharge protection

US10256775B2|2019-04-09|Semiconductor device including an ESD protective element

JP2005244850A|2005-09-08|High frequency switch apparatus

FR3066059A1|2018-11-09|COMMUNICATION APPARATUS WITH RECEIVING CHAIN WITH REDUCED DIMENSIONS

US20200220503A1|2020-07-09|Low noise amplifier and semiconductor device

US9203396B1|2015-12-01|Radio frequency switch device with source-follower

US20080001650A1|2008-01-03|Controlling output current delivered by a transistor

同族专利:

公开号 | 公开日

KR20150092011A|2015-08-12|

FR3017261B1|2018-05-18|

CN104821811B|2019-05-03|

TWI647910B|2019-01-11|

CN104821811A|2015-08-05|

TW201532388A|2015-08-16|

US20150222259A1|2015-08-06|

US9379698B2|2016-06-28|

JP2015149720A|2015-08-20|

引用文献:

公开号 | 申请日 | 公开日 | 申请人 | 专利标题

US3551788A|1968-09-13|1970-12-29|Servo Corp Of America|High voltage transistorized stack with leakage current compensation|

US3699359A|1971-04-20|1972-10-17|Philco Ford Corp|Electronic latching device|

US4053916B1|1975-09-04|1983-03-08|

FR2430092B1|1978-06-29|1980-11-28|Ibm France|

DE2851789C2|1978-11-30|1981-10-01|Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt|Circuit for switching and transmitting alternating voltages|

US4491750A|1982-09-28|1985-01-01|Eaton Corporation|Bidirectionally source stacked FETs with drain-referenced common gating|

US5313083A|1988-12-16|1994-05-17|Raytheon Company|R.F. switching circuits|

US5105164A|1989-02-28|1992-04-14|At&T Bell Laboratories|High efficiency uhf linear power amplifier|

US5012123A|1989-03-29|1991-04-30|Hittite Microwave, Inc.|High-power rf switching system|

JP2922030B2|1991-09-18|1999-07-19|松下電子工業株式会社|Variable resistance integrated circuit device|

JP3243892B2|1993-05-21|2002-01-07|ソニー株式会社|Signal switch|

US5973382A|1993-07-12|1999-10-26|Peregrine Semiconductor Corporation|Capacitor on ultrathin semiconductor on insulator|

US5416043A|1993-07-12|1995-05-16|Peregrine Semiconductor Corporation|Minimum charge FET fabricated on an ultrathin silicon on sapphire wafer|

US5572040A|1993-07-12|1996-11-05|Peregrine Semiconductor Corporation|High-frequency wireless communication system on a single ultrathin silicon on sapphire chip|

US5973363A|1993-07-12|1999-10-26|Peregrine Semiconductor Corp.|CMOS circuitry with shortened P-channel length on ultrathin silicon on insulator|

US5930638A|1993-07-12|1999-07-27|Peregrine Semiconductor Corp.|Method of making a low parasitic resistor on ultrathin silicon on insulator|

US5863823A|1993-07-12|1999-01-26|Peregrine Semiconductor Corporation|Self-aligned edge control in silicon on insulator|

US5452473A|1994-02-28|1995-09-19|Qualcomm Incorporated|Reverse link, transmit power correction and limitation in a radiotelephone system|

US5553295A|1994-03-23|1996-09-03|Intel Corporation|Method and apparatus for regulating the output voltage of negative charge pumps|

JP2801563B2|1994-08-30|1998-09-21|松下電器産業株式会社|Transmission / reception circuit of communication radio, semiconductor integrated circuit device, and communication radio|

FR2742942B1|1995-12-26|1998-01-16|Sgs Thomson Microelectronics|HIGH VOLTAGE SLOT GENERATOR|

US5777530A|1996-01-31|1998-07-07|Matsushita Electric Industrial Co., Ltd.|Switch attenuator|

JP3484462B2|1996-04-11|2004-01-06|株式会社ルネサステクノロジ|Method for estimating lifetime of floating SOI-MOSFET|

KR100418001B1|1996-08-05|2004-02-11|미쓰비시덴키 가부시키가이샤|High-frequency integrated circuit for high-frequency radio transmitter-receiver suppressed in influence of high-frequency power leakage|

US5818099A|1996-10-03|1998-10-06|International Business Machines Corporation|MOS high frequency switch circuit using a variable well bias|

US5920233A|1996-11-18|1999-07-06|Peregrine Semiconductor Corp.|Phase locked loop including a sampling circuit for reducing spurious side bands|

JP3441330B2|1997-02-28|2003-09-02|株式会社東芝|Semiconductor device and manufacturing method thereof|

US6160292A|1997-04-23|2000-12-12|International Business Machines Corporation|Circuit and methods to improve the operation of SOI devices|

US5994207A|1997-05-12|1999-11-30|Silicon Genesis Corporation|Controlled cleavage process using pressurized fluid|

US6033974A|1997-05-12|2000-03-07|Silicon Genesis Corporation|Method for controlled cleaving process|

WO1999010927A1|1997-08-29|1999-03-04|Farrens Sharon N|In situ plasma wafer bonding method|

US6100159A|1997-11-06|2000-08-08|Advanced Micro Devices, Inc.|Quasi soi device|

JP3711193B2|1998-01-16|2005-10-26|三菱電機株式会社|Transmission / reception switching circuit|

US5959488A|1998-01-24|1999-09-28|Winbond Electronics Corp.|Dual-node capacitor coupled MOSFET for improving ESD performance|

US6271067B1|1998-02-27|2001-08-07|Micron Technology, Inc.|Methods of forming field effect transistors and field effect transistor circuitry|

US6249027B1|1998-06-08|2001-06-19|Sun Microsystems, Inc.|Partially depleted SOI device having a dedicated single body bias means|

JP2000022160A|1998-07-06|2000-01-21|Hitachi Ltd|Semiconductor integrated circuit and fabrication thereof|

JP4360702B2|1998-08-07|2009-11-11|株式会社ルネサステクノロジ|Semiconductor device|

JP2000077992A|1998-09-01|2000-03-14|Kawasaki Steel Corp|Analog switch|

JP3408762B2|1998-12-03|2003-05-19|シャープ株式会社|Semiconductor device having SOI structure and method of manufacturing the same|

US6111455A|1998-12-30|2000-08-29|International Business Machines Corporation|Method for controlling delays in silicon on insulator circuits|

US6171965B1|1999-04-21|2001-01-09|Silicon Genesis Corporation|Treatment method of cleaved film for the manufacture of substrates|

US6816016B2|2000-08-10|2004-11-09|Tropian, Inc.|High-efficiency modulating RF amplifier|

EP1212787B1|1999-08-10|2014-10-08|Silicon Genesis Corporation|A cleaving process to fabricate multilayered substrates using low implantation doses|

US6229187B1|1999-10-20|2001-05-08|Advanced Micro Devices, Inc.|Field effect transistor with non-floating body and method for forming same on a bulk silicon wafer|

US6376286B1|1999-10-20|2002-04-23|Advanced Micro Devices, Inc.|Field effect transistor with non-floating body and method for forming same on a bulk silicon wafer|

JP3608456B2|1999-12-08|2005-01-12|セイコーエプソン株式会社|Manufacturing method of SOI structure MIS field effect transistor|

US6225667B1|2000-01-18|2001-05-01|Advanced Micro Devices, Inc.|Leaky lower interface for reduction of floating body effect in SOI devices|

US6504212B1|2000-02-03|2003-01-07|International Business Machines Corporation|Method and apparatus for enhanced SOI passgate operations|

JP3504212B2|2000-04-04|2004-03-08|シャープ株式会社|Semiconductor device with SOI structure|

US6288613B1|2000-06-15|2001-09-11|Nortel Networks Limited|Bias circuits for depletion mode field effect transistors|

JP2002033399A|2000-07-13|2002-01-31|Toshiba Corp|Semiconductor integrated circuit and its manufacturing method|

US6503783B1|2000-08-31|2003-01-07|Micron Technology, Inc.|SOI CMOS device with reduced DIBL|

US6496074B1|2000-09-28|2002-12-17|Koninklijke Philips Electronics N.V.|Cascode bootstrapped analog power amplifier circuit|

US6978437B1|2000-10-10|2005-12-20|Toppan Photomasks, Inc.|Photomask for eliminating antenna effects in an integrated circuit and integrated circuit manufacture with same|

JP4434474B2|2000-11-29|2010-03-17|Ｎｅｃエレクトロニクス株式会社|MOS transistor simulation test method|

US6785703B2|2001-05-24|2004-08-31|International Business Machines Corporation|Simultaneous dual rail static carry-save-adder circuit using silicon on insulator technology|

US6819938B2|2001-06-26|2004-11-16|Qualcomm Incorporated|System and method for power control calibration and a wireless communication device|

KR100906356B1|2001-08-10|2009-07-06|히타치 긴조쿠 가부시키가이샤|Bypass filter|

JP3986780B2|2001-08-17|2007-10-03|三菱電機株式会社|Complementary push-pull amplifier|

US7796969B2|2001-10-10|2010-09-14|Peregrine Semiconductor Corporation|Symmetrically and asymmetrically stacked transistor group RF switch|

US6804502B2|2001-10-10|2004-10-12|Peregrine Semiconductor Corporation|Switch circuit and method of switching radio frequency signals|

JP3813869B2|2001-12-20|2006-08-23|松下電器産業株式会社|Field effect transistor switch circuit|

JP3947044B2|2002-05-31|2007-07-18|富士通株式会社|I / O buffer|

US6642578B1|2002-07-22|2003-11-04|Anadigics, Inc.|Linearity radio frequency switch with low control voltage|

JP3445608B2|2002-10-25|2003-09-08|株式会社東芝|Digital information management system including video information|

JP2004205301A|2002-12-25|2004-07-22|Nec Corp|Evaluation device and circuit designing method used therefor|

CN1256521C|2003-03-26|2006-05-17|浙江大学|Frequency converter volume variable speed closed hydraulic control systems|

JP4257971B2|2003-03-27|2009-04-30|独立行政法人産業技術総合研究所|Method for applying gate signal of double gate field effect transistor|

US6930357B2|2003-06-16|2005-08-16|Infineon Technologies Ag|Active SOI structure with a body contact through an insulator|

JP4342970B2|2004-02-02|2009-10-14|株式会社東芝|Semiconductor memory device and manufacturing method thereof|

US7042044B2|2004-02-18|2006-05-09|Koucheng Wu|Nor-type channel-program channel-erase contactless flash memory on SOI|

US7072217B2|2004-02-24|2006-07-04|Micron Technology, Inc.|Multi-state memory cell with asymmetric charge trapping|

US7291896B2|2004-06-24|2007-11-06|Rajendran Nair|Voltage droop suppressing active interposer|

US7319357B2|2004-08-24|2008-01-15|Texas Instruments Incorporated|System for controlling switch transistor performance|

JP2006073627A|2004-08-31|2006-03-16|Toshiba Corp|Semiconductor integration device|

US7158067B2|2005-01-31|2007-01-02|The United States Of America As Represented By The Secretary Of The Navy|Analog to digital converter using sawtooth voltage signals with differential comparator|

US7402850B2|2005-06-21|2008-07-22|Micron Technology, Inc.|Back-side trapped non-volatile memory device|

US8742502B2|2005-07-11|2014-06-03|Peregrine Semiconductor Corporation|Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction|

US20080076371A1|2005-07-11|2008-03-27|Alexander Dribinsky|Circuit and method for controlling charge injection in radio frequency switches|

US7910993B2|2005-07-11|2011-03-22|Peregrine Semiconductor Corporation|Method and apparatus for use in improving linearity of MOSFET's using an accumulated charge sink|

US7890891B2|2005-07-11|2011-02-15|Peregrine Semiconductor Corporation|Method and apparatus improving gate oxide reliability by controlling accumulated charge|

US20070023833A1|2005-07-28|2007-02-01|Serguei Okhonin|Method for reading a memory cell having an electrically floating body transistor, and memory cell and array implementing same|

US8159283B2|2005-08-09|2012-04-17|Hitachi Metals, Ltd.|High frequency switch circuit comprising a transistor on the high frequency path|

US7265041B2|2005-12-19|2007-09-04|Micrel, Inc.|Gate layouts for transistors|

KR100662848B1|2005-12-20|2007-01-02|삼성전자주식회사|Inductor integrated chip and fabrication method thereof|

JP4342569B2|2007-04-17|2009-10-14|株式会社東芝|High frequency switch circuit|

US7863691B2|2008-03-10|2011-01-04|International Business Machines Corporation|Merged field effect transistor cells for switching|

US8526883B2|2008-06-13|2013-09-03|Nxp, B.V.|RF switch for an RF splitter|

US7994577B2|2008-07-18|2011-08-09|Taiwan Semiconductor Manufacturing Company, Ltd.|ESD protection structures on SOI substrates|

JP2010109233A|2008-10-31|2010-05-13|Renesas Technology Corp|Semiconductor device|

JP2010183455A|2009-02-06|2010-08-19|Hitachi Ulsi Systems Co Ltd|Semiconductor device|

JP2010220200A|2009-02-19|2010-09-30|Renesas Electronics Corp|Conduction switching circuit, conduction switching circuit block, and operation method for conduction switching circuit|

US8723260B1|2009-03-12|2014-05-13|Rf Micro Devices, Inc.|Semiconductor radio frequency switch with body contact|

US8395435B2|2009-07-30|2013-03-12|Qualcomm, Incorporated|Switches with bias resistors for even voltage distribution|

US8385845B1|2009-10-09|2013-02-26|Triquint Semiconductor, Inc.|Shunt device for switch|

US8970278B2|2010-04-27|2015-03-03|Rf Micro Devices, Inc.|High power FET switch|

US8179205B2|2010-05-21|2012-05-15|Samsung Electro-Mechanics|Linearization systems and methods for variable attenuators|

US20130252562A1|2010-09-21|2013-09-26|Dsp Group, Ltd.|High power high isolation low current cmos rf switch|

US8462473B2|2010-12-21|2013-06-11|Microchip Technology Incorporated|Adaptive electrostatic discharge protection circuit|

US8886136B1|2011-04-22|2014-11-11|Marvell International Ltd.|Two-pin TR switch with switched capacitor|

US20130029614A1|2011-07-29|2013-01-31|Samsung Electro-Mechanics Company|Systems, Methods, and Apparatuses for Negative-Charge-Pump-Based Antenna Switch Controllers Utilizing Battery Supplies|

JP5827065B2|2011-08-08|2015-12-02|スパンションエルエルシー|Semiconductor device and voltage dividing circuit|

US8649137B2|2011-10-20|2014-02-11|Semiconductor Components Industries, Llc|Semiconductor device and method of forming same for ESD protection|

JP5596727B2|2012-03-09|2014-09-24|旭化成エレクトロニクス株式会社|Non-inverting buffer circuit|

US8829967B2|2012-06-27|2014-09-09|Triquint Semiconductor, Inc.|Body-contacted partially depleted silicon on insulator transistor|

US9160328B2|2012-07-07|2015-10-13|Skyworks Solutions, Inc.|Circuits, devices, methods and applications related to silicon-on-insulator based radio-frequency switches|

US8729952B2|2012-08-16|2014-05-20|Triquint Semiconductor, Inc.|Switching device with non-negative biasing|

US8847672B2|2013-01-15|2014-09-30|Triquint Semiconductor, Inc.|Switching device with resistive divider|

US9214932B2|2013-02-11|2015-12-15|Triquint Semiconductor, Inc.|Body-biased switching device|

US8977217B1|2013-02-20|2015-03-10|Triquint Semiconductor, Inc.|Switching device with negative bias circuit|

JP5575348B1|2014-01-20|2014-08-20|株式会社Ｌｅａｐ|Connector manufacturing method|TWI580185B|2015-03-05|2017-04-21|瑞昱半導體股份有限公司|Analog switch circuit|

EP3297161B1|2016-09-15|2019-08-21|Visic Technologies Ltd.|Power device for high voltage and high current switching|

KR101901699B1|2016-10-05|2018-09-28|삼성전기 주식회사|Antenna switch circuit with improved harmonic suppression characteristic|

US10778206B2|2018-03-20|2020-09-15|Analog Devices Global Unlimited Company|Biasing of radio frequency switches for fast switching|

KR102112794B1|2019-03-25|2020-05-19|주식회사 레오엘에스아이|Switching circuits|

US11152917B1|2020-05-28|2021-10-19|Analog Devices International Unlimited Company|Multi-level buffers for biasing of radio frequency switches|

法律状态:
2015-12-08| PLFP| Fee payment|Year of fee payment: 2 |

2016-12-15| PLFP| Fee payment|Year of fee payment: 3 |

2017-08-11| PLSC| Search report ready|Effective date: 20170811 |

2017-12-11| PLFP| Fee payment|Year of fee payment: 4 |

2018-12-13| PLFP| Fee payment|Year of fee payment: 5 |

2019-12-16| PLFP| Fee payment|Year of fee payment: 6 |

2021-10-08| ST| Notification of lapse|Effective date: 20210905 |

优先权:

申请号 | 申请日 | 专利标题

US14/172,727|2014-02-04|

US14/172,727|US9379698B2|2014-02-04|2014-02-04|Field effect transistor switching circuit|

[返回顶部]